 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| as3930 single channel low frequency wakeup receiver www.austriamicrosystems.com/as3930 revision 1.0 1 - 33 data sheet 1 general description the as3930 is a single-c hannel low power ask re ceiver that is able to generate a wakeup upon detection of a data signal which uses a lf carrier frequency between 110 - 150 khz. the integrated correlator can be used for detection of a programmable 16-bit wakeup pattern. the as3930 provides a digital rssi value, it supports a programmable data rate and manchester decoding with clock recovery. the as3930 offers a real-t ime clock (rtc), which is either derived from a crystal oscillator or the internal rc oscillator. the programmable features of as3930 enable to optimize its settings for achieving a longer distance while retaining a reliable wakeup generation. the sensitivity level of as3930 can be adjusted in presence of a strong field or in noisy environments. the device is available in 16 pin tssop and qfn 4x4 16 ld packages. 2 key features single channel ask wakeup receiver carrier frequency range 110 - 150 khz programmable wakeup pattern (16bits) doubling of wakeup pattern supported wakeup without pattern detection supported wakeup sensitivity 100vrms (typ.) adjustable sensitivity level highly resistant to false wakeups false wakeup counter periodical forced wakeup supported (1s ? 2h) low power listening modes current consumption in listening mode 1.37 a (typ.) data rate adjustable from 0.5 - 4 kbps (manchester) manchester decoding with clock recovery digital rssi dynamic range 64db 5 bit rssi step (2db per step) rtc based on 32khz xtal, rc-osc, or external clock operating temperature range -40 to +85oc operating supply voltage 2.4 - 3.6v (ta = 25oc) bidirectional serial digital interface (sdi) package option 16 pin tssop, qfn 4x4 16 ld 3 applications the as3930 is ideal for active rfid tags, real-time location systems, operator identification, access control, and wireless sensors.
www.austriamicrosystems.com/as3930 revision 1.0 2 - 33 as3930 data sheet - applications figure 1. as3930 typical application diagram with crystal oscillator figure 2. as3930 typical application diagram without crystal oscillator vcc lfp nc nc lfn vss gnd xin xout wake dat cl_dat cs scl sdi sdo vcc cbat xtal cl tx transmitter as3930 transmitting antenna vcc lfp nc nc lfn vss gnd xin xout wake dat cl_dat cs scl sdi sdo vcc cbat tx transmitter as3930 transmitting antenna www.austriamicrosystems.com/as3930 revision 1.0 3 - 33 as3930 data sheet - applications figure 3. as3930 typical application diagram with clock from external source vcc lfp nc nc lfn vss gnd xin xout wake dat cl_dat cs scl sdi sdo vcc cbat tx transmitter as3930 transmitting antenna r c external clock www.austriamicrosystems.com/as3930 revision 1.0 4 - 33 as3930 data sheet - contents contents 1 general description............................................................................................................ ........................................................ 1 2 key features ................................................................................................................... ............................................................ 1 3 applications ................................................................................................................... ............................................................. 1 4 pin assignments................................................................................................................ ......................................................... 5 4.1 tssop package .................................................................................................................. .................................................................... 5 4.1.1 pin descriptions........................................................................................................ .................................................................... 5 4.2 qfn package .................................................................................................................... ....................................................................... 6 4.2.1 pin descriptions........................................................................................................ .................................................................... 6 5 absolute maximum ratings....................................................................................................... ................................................ 7 6 electrical characteristics..................................................................................................... ...................................................... 8 7 typical operating characteristics.............................................................................................. ............................................. 10 8 detailed description ........................................................................................................... ....................................................... 11 8.1 block diagram .................................................................................................................. ...................................................................... 11 8.2 operating modes ................................................................................................................ .................................................................... 12 8.2.1 power down mode ......................................................................................................... ............................................................ 12 8.2.2 listening mode .......................................................................................................... ................................................................. 12 8.2.3 preamble detection / pattern correlation ................................................................................ ................................................... 12 8.2.4 data receiving .......................................................................................................... ................................................................. 13 8.3 system and block specification ................................................................................................. ............................................................ 13 8.3.1 main logic and sdi ...................................................................................................... .............................................................. 13 8.4 channel amplifier and frequency detector....................................................................................... ..................................................... 18 8.4.1 frequency detector / agc ................................................................................................ ......................................................... 18 8.4.2 antenna damper.......................................................................................................... ............................................................... 19 8.5 demodulator / data slicer ...................................................................................................... ................................................................ 19 8.6 correlator..................................................................................................................... ........................................................................... 20 8.7 wakeup protocol - carrier frequency 125 khz .................................................................................... .................................................. 23 8.7.1 without pattern detection (manchester decoder disabled) ................................................................. ........................................ 23 8.7.2 single pattern detection (manchester decoder disabled) .................................................................. ........................................ 23 8.7.3 single pattern detection (manchester decoder enabled) ................................................................... ........................................ 25 8.8 false wakeup register .......................................................................................................... ................................................................ 25 8.9 real time clock (rtc).......................................................................................................... ................................................................. 26 8.9.1 crystal oscillator...................................................................................................... ................................................................... 27 8.9.2 rc-oscillator ........................................................................................................... ................................................................... 27 8.9.3 external clock source ................................................................................................... ............................................................. 27 9 package drawings and markings.................................................................................................. .......................................... 29 10 ordering information........................................................................................................... ................................................... 33 www.austriamicrosystems.com/as3930 revision 1.0 5 - 33 as3930 data sheet - pin assignments 4 pin assignments 4.1 tssop package figure 4. pin assignments 16 pin tssop package 4.1.1 pin descriptions table 1. pin descriptions 16 pin tssop package pin name pin number pin type description cs 1 di chip select scl 2 di sdi interface clock sdi 3 di sdi data input sdo 4 do_t sdi data output (tristate when cs is low) v cc 5 s positive supply voltage gnd 6 s negative supply voltage nc 7 not connected nc 8 not connected lfp 9 aio input antenna lfn 10 aio antenna ground xin 11 aio crystal oscillator input xout 12 aio crystal oscillator output v ss 13 s substrate wake 14 do wakeup output irq dat 15 do data output cl_dat 16 do manchester recovered clock as3930 1 2 3 4 5 6 7 12 16 15 14 13 scl sdi sdo v cc gnd nc dat wake v ss xout xin lfn 11 10 cs cl_dat 8 9 nc lfp www.austriamicrosystems.com/as3930 revision 1.0 6 - 33 as3930 data sheet - pin assignments 4.2 qfn package figure 5. pin assignments qfn 4x4 16 ld package 4.2.1 pin descriptions note: pin types: s: supply pad aio: analog i/o di: digital input do: digital output do_t: digital output / tristate table 2. pin descriptions qfn 4x4 16 ld package pin name pin number pin type description nc 1 not connected nc 2 not connected lfp 3 aio input antenna lfn 4 aio antenna ground xin 5 aio crystal oscillator input xout 6 aio crystal oscillator output v ss 7 s substrate wake 8 do wakeup output irq dat 9 do data output cl_dat 10 do manchester recovered clock cs 11 di chip select scl 12 di sdi interface clock sdi 13 di sdi data input sdo 14 do_t sdi data output (tristate when cs is low) v cc 15 s positive supply voltage gnd 16 s negative supply voltage as3930 nc lfn nc cs dat xin sdi lfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xout v ss wake cl_dat scl sdo v cc gnd www.austriamicrosystems.com/as3930 revision 1.0 7 - 33 as3930 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 8 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units notes dc supply voltage (v dd )-0.55v input pin voltage (v in )-0.55v input current (latch up immunity) (i source ) -100 100 ma norm: jedec 78 electrostatic discharge (esd) 2 kv norm: mil 883 e method 3015 (hbm) total power dissipation (all supplies and outputs) (p t ) 0.07 mw storage temperature (t strg ) -65 150 oc package body temperature (t body ) 260 oc norm: ipc/jedec j-std-020c 1 1. the reflow peak soldering temperature (body temperature) is sp ecified according ipc/jedec j-std- 020c ?moisture/reflow sensiti vity classification for nonhermetic solid state surface mount devices?. humidity non-condensing 5 85 % www.austriamicrosystems.com/as3930 revision 1.0 8 - 33 as3930 data sheet - electrical characteristics 6 electrical characteristics table 4. electrical characteristics symbol parameter conditions min typ max units operating conditions av dd positive supply voltage 2.4 3.6 v av ss negative supply voltage 0 0 v t amb ambient temperature -40 85 oc dc/ac characteristics for digital inputs and outputs cmos input v ih high level input voltage 0.58 * v dd 0.7 * v dd 0.83 * v dd v v il low level input voltage 0.125 * v dd 0.2 * v dd 0.3 * dvdd v i leak input leakage current 100 na cmos output v oh high level output voltage with a load current of 1ma v dd - 0.4 v v ol low level output voltage with a load current of 1ma v ss + 0.4 v c l capacitive load for a clock frequency of 1 mhz 400 pf tristate cmos output v oh high level output voltage with a load current of 1ma v dd - 0.4 v v ol low level output voltage with a load current of 1ma v ss + 0.4 v i oz tristate leakage current to dvdd and dvss 100 na table 5. electrical system specifications symbol parameter conditions min typ max units input characteristics rin input impedance in case no antenna damper is set (r1<4>=0) 2 m fmin minimum input frequency 110 khz fmax maximum input frequency 150 khz current consumption ipwd power down mode 400 800 na ichrc current consumption in standard listening mode with channel active all the time and rc-oscillator as rtc 2.7 a ichoorc current consumption in on/ off mode and rc-oscillator as rtc 11% duty cycle 1.37 a 50% duty cycle 2 ichxt current consumption in standard listening mode and crystal oscillator as rtc 3.5 5.9 a www.austriamicrosystems.com/as3930 revision 1.0 9 - 33 as3930 data sheet - electrical characteristics idata current consumption in preamble detection / pattern correlation / data receiving mode (rc-oscillator) with 125 khz carrier frequency and 1 kbps data-rate. no load on the output pins. 5.3 9 a input sensitivity sens input sensitivity on all channels with 125khz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 vrms channel settling time tsamp amplifier settling time 250 s crystal oscillator fxtal frequency crystal dependent 32.768 khz txtal start-up time crystal dependent 1 s ixtal current consumption 1 a external clock source iextcl current consumption 1 a rc oscillator frcncal frequency if no calibration is performed 27 32.768 42 khz frccal32 frequency if calibration with 32.768 khz reference signal is performed 31 32.768 34.5 khz frccalmax frequency maximum achievable frequency after calibration 35 khz frccalmin frequency minimum achievable frequency after calibration 30 khz tcalrc calibration time 65 periods of reference clock irc current consumption 200 na table 5. electrical system specifications symbol parameter conditions min typ max units www.austriamicrosystems.com/as3930 revision 1.0 10 - 33 as3930 data sheet - typical operating characteristics 7 typical operating characteristics figure 6. sensitivity over voltage and temperature figure 7. sensitivity over rssi figure 8. rc-osc frequency over voltage (calibr.) figure 9. rc-osc frequency over temperature (calibr.) v in = 2.4v v in = 1.5v v in = 1.0v 0 20 40 60 80 100 120 2.4 3 3.6 supply voltage [v] sensitivity [vrms] -40 o c 27 o c 95 o c 1 10 100 1000 10000 100000 1000000 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 rssi [db] input voltage [vrms] 31 31.5 32 32.5 33 33.5 34 34.5 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage [v] rc-osc frequency [khz] 31 31.5 32 32.5 33 33.5 34 34.5 -36-30-20-10 0 102030405060708090 operating temperature [ o c] rc-osc frequency [khz] www.austriamicrosystems.com/as3930 revision 1.0 11 - 33 as3930 data sheet - detailed description 8 detailed description the as3930 is a one-dimensional low power low-frequency wakeup receiver. the as3930 is capable to detect the presence of an ind uctive coupled carrier and extract the envelope of the on-off-keying (ook) modulated carrier. in case the carrier is manchester coded the clock is recovered from the transmitted signal and the data can be correlated with a programmed pattern. if the detected pattern corresp onds to the stored one, a wake-up signal (irq) is risen up. the pattern correlation can be bypassed in case and the wake-up detection is ba sed only on the frequency detection. the as3930 is made up of a single receiving channel, one envelop detector, one data correlator, one manchester decoder, 8 progr ammable registers with the main logic and a real time clock. the digital logic can be accessed by an sdi. the real time clock can be based on a crystal oscillator or on an internal rc. in case internal rc is used to improve its accuracy a calibration can be performed. 8.1 block diagram figure 10. block diagram lf1p lfn gnd x in x out cl_dat dat cs sdo sdi scl irq vcc rssi channel amplifier wakeup main logic sdi envelope detector / data slicer correlator manchester decoder i/v bias xtal rtc rc rtc as3930 www.austriamicrosystems.com/as3930 revision 1.0 12 - 33 as3930 data sheet - detailed description as3930 needs the following external components: power supply capacitor - cbat ? 100 nf 32.768 khz crystal with its two pulling capacitors ? xtal and cl (it is possible to omit these components if the internal rc os cillator is used instead of the crystal oscillator). input lc resonator. in case the internal rc-oscillator is used (no crystal oscillator is mounted), the pin xin has to be connected to the supply, w hile pin xout should stay floating. application diagrams with and without crystal are shown in figure 1 and figure 2 8.2 operating modes 8.2.1 power down mode in power down mode as3930 is completely switched off. the typical current consumption is 400 na. 8.2.2 listening mode in listening mode only the channel amplifier and the rtc are running. in this mode the system detects the presence of a carrier . in case the carrier is detected the rssi can be displayed. inside this mode it is possible to distinguish the following three sub modes: 8.2.2.1 standard listening mode the channel amplifier, capable to detect the presence of the carrier frequency, is active all the time. 8.2.2.2 on/off mode (low power mode) the channel amplifier is active for one millisecond to be than switched-off for a certain time. the off-time is programmable se e r4<7:6> . figure 11. on/off mode for both sub modes it is possible to enable a further feature called artificial wake-up. if the artificial wakeup is enabled th e as3930 produces an interrupt after a certain time regardless whether any activity is detected on the input. the period of the artificial wake-up i s defined in the register r8<2:0>. the user can distinguish between artificial wake-up and wake-up based on the field detection (frequency or pattern det ection) since the artificial wake-up interrupt lasts only 128 s. with this interrupt the microcontroller ( c) can get feedback on the surrounding environment (e.g. read the false wakeup register, see relator register r13<7:0>) and/or take actions in order to change the setup. 8.2.3 preamble detection / pattern correlation the chip can go in to this mode after detecting a lf carrier only if the data correlator function is enabled see r1<1> . the correlator searches first for preamble frequency (constant frequency of manchester clock defined according to bit-rate transmission) and then for d ata pattern. if the pattern is matched the wake-up interr upt is displayed on the wake output and the chip goes in data receiving mode. if th e pattern fails the internal wake-up is terminated and no irq is produced. channel presence of carrier t0 t0 + 1ms t0 + t t0 + t + 1ms t0 + 2t time time www.austriamicrosystems.com/as3930 revision 1.0 13 - 33 as3930 data sheet - detailed description 8.2.4 data receiving the user can enable this mode allowing the pattern correlation or just on the base of the frequency detection. in this mode the chip can be retained as a normal ook receiver. the data is provided on the dat pin and in case the manchester decoder is enabled see r1<3> , the recovered clock is present on the cl_dat. it is possible to put the chip back to listening mode either with a direct command (c lear_wake (see table 12) ) or by using the timeout feature. this feature automatically sets the chip back to listening mode after a certain time defined in the r7<7:5> . 8.3 system and bl ock specification 8.3.1 main logic and sdi 8.3.1.1 register table 8.3.1.2 register table description and default values table 6. register table 7 6 5 4 3 2 1 0 r0 n.a. on_off reserved en_a pwd r1 abs_hy agc_tlim agc_ud att_on en _manch en_pat2 en_wpat en_rtc r2 s_absh w_pat_t<1:0> reserved s_wu1<1:0> r3 hy_20m hy_pos fs_slc<2:0> fs_env<2:0> r4 t_off<1:0> r_val<1:0> gr<3:0> r5 ts2<7:0> r6 ts1<7:0> r7 t_out<2:0> t_hbit<4:0> r8 n.a. t_auto<2:0> r9 n.a. reserved r10 n.a. rssi1<4:0> r11 n.a. rssi3<4:0> r12 n.a. rssi2<4:0> r13 f_wake table 7. default values of registers register name type default value description r0<5> on_off w 0 on/off operation mode. (duty-cycle defined in the register r4<7:6>) r0<4> mux_123 w 0 reserved (it is not allowed to set this bit to 1) r0<3> reserved w 1 reserved r0<2> reserved w 1 reserved r0<1> en_a w 1 channel enable r0<0> pwd w 0 power down r1<7> abs_hy w 0 data slicer absolute reference r1<6> agc_tlim w 0 agc acting only on the first carrier burst r1<5> agc_ud w 1 agc operating in both direction (up-down) r1<4> att_on w 0 antenna damper enable r1<3> en_manch w 0 manchester decoder enable www.austriamicrosystems.com/as3930 revision 1.0 14 - 33 as3930 data sheet - detailed description r1<2> en_pat2 w 0 double wakeup pattern correlation r1<1> en_wpat w 1 data correlation enable r1<0> en_rtc w 1 crystal oscillator enable r2<7> s_absh w 0 data slicer threshold reduction r2<6:5> w_pat w 00 pattern correlation tolerance (see table 19) r2<4:2> 000 reserved r2<1:0> s_wu1 w 00 tolerance setting for the stage wakeup (see table 13) r3<7> hy_20m w 0 data slicer hysteresis if hy_20m = 0 then comparator hysteresis = 40mv if hy_20m = 1 then comparator hysteresis = 20mv r3<6> hy_pos w 0 data slicer hysteresis only on positive edges (hy_pos=0, hysteresis on both edges, hy_pos=1, hysteresis only on positive edges) r3<5:3> fs_scl w 100 data slices time constant (see table 17) r3<2:0> fs_env w 000 envelop detector time constant (see table 16) r4<7:6> t_off w 00 off time in on/off operation mode t_off=00 1ms t_off=01 2ms t_off=10 4ms t_off=11 8ms r4<5:4> d_res w 01 antenna damping resistor (see table 15) r4<3:0> gr w 0000 gain reduction (see table 14) r5<7:0> ts2 w 01101001 2 nd byte of wakeup pattern r6<7:0> ts1 w 10010110 1 st byte of wakeup pattern r7<7:5> t_out w 000 automatic time-out (see table 20) r7<4:0> t_hbit w 01011 bit rate definition (see table 18) r8<2:0> t_auto w 000 artificial wake-up t_auto=000 no artificial wake-up t_auto=001 1 sec t_auto=010 5 sec t_auto=011 20 sec t_auto=100 2 min t_auto=101 15min t_auto=110 1 hour t_auto=111 2 hour r9<6:0> 000000 reserved r10<4:0> rssi r rssi channel r11<4:0> reserved table 7. default values of registers register name type default value description www.austriamicrosystems.com/as3930 revision 1.0 15 - 33 as3930 data sheet - detailed description 8.3.1.3 serial data interface (sdi) this 4-wire interface is used by the microcontroller (c) to program the as3930. the maximum clock operation frequency of the s di is 2 mhz. note: sdo is set to tristate if cs is low. in this way mo re than one device can communicate on the same sdo bus. sdi command structure to program the sdi the cs signal has to go high. a sdi command is made up by a two bytes serial command and the data is sampled on the falling edge of sclk. the table 9 shows how the command looks like, from the msb (b15) to lsb (b0). the command stream has to be sent to the sdi from the msb (b15) to the lsb (b0). the first two bits (b15 and b14) define the operating mode. there are three modes available (write, read, direct command) plus one spare (not used), as shown in table 10 . in case a write or read command happens the next 5 bits (b13 to b9) define the register address which has to be written respect ively read, as shown in table 11 . r12<4:0> reserved r13<7:0> f_wak wr false wakeup register table 8. serial data interface (sdi) pins name signal signal level description cs digital input with pull down cmos chip select sdi digital input with pull down cmos serial data input for writing registers, data to transmit and/or writing addresses to select readable register sdo digital output cmos serial data output for received data or read value of selected registers sclk digital input with pull down cmos clock for serial data read and write table 9. sdi command structure mode register address / direct command register data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 10. sdi command structure b15 b14 mode 00 write 0 1 read 1 0 not allowed 1 1 direct command table 11. sdi command structure b13 b12 b11 b10 b9 b8 read/write register 000000 r0 000001 r1 000010 r2 000011 r3 table 7. default values of registers register name type default value description www.austriamicrosystems.com/as3930 revision 1.0 16 - 33 as3930 data sheet - detailed description the last 8 bits are the data that has to be written respectively read. a cs toggle high-low-high terminates the command mode. if a direct command is sent (b15-b14=11) the bits from b13 to b9 defines the direct command while the last 8 bits are omitted. the table 12 shows all possible direct commands: all direct commands are explained below: - clear_wake: clears the wake state of the chip. in case the chip has woken up (wake pin is high) the chip is set back to listen ing mode - reset_rssi: resets the rssi measurement. - trim_osc: starts the trimming procedure of the internal rc oscillator (see figure 21 ) - clear_false: resets the false wakeup register (r13=00) - preset_default: sets all register in the default mode, as shown in figure 7 note: in order to get the as3930 work properly after sending the preset_default direct command, it is mandatory to write the r0<3:2>= 00 writing of data to addressable registers ( write mode) the sdi is sampled at the falling edge of clk (as shown in the following diagrams). a cs toggling high-low-high indicates the end of the write command after register has been written. the following example shows a write command. 000100 r4 000101 r5 000110 r6 000111 r7 001000 r8 001001 r9 001010 r10 001011 r11 001100 r12 001101 r13 table 12. list of direct commands command_mode b13 b12 b11 b10 b9 b8 clear_wake 000000 reset_rssi 000001 trim_osc 000010 clear_false 000011 preset_default 000100 table 11. sdi command structure b13 b12 b11 b10 b9 b8 read/write register www.austriamicrosystems.com/as3930 revision 1.0 17 - 33 as3930 data sheet - detailed description figure 12. writing of a single byte (falling edge sampling) figure 13. writing of register data with auto-incrementing address reading of data from addressable registers ( read mode) once the address has been sent through sdi, the data can be fed through the sdo pin out to the microcontroller. a cs low toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the read command and prepare the interface to the next command control byte. to transfer bytes from consecutive addresses, sdi master has to keep the cs signal high and the sclk clock has to be active as long as data need to be read. figure 14. reading of a single register byte cs sclk sdi 0 0 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 x x s clk raising e dge data is transf ered from c sclk falling edge data is sampled data is moved t o a ddress a5-a 0 cs falling ed ge signals e nd of write mode two le ading zeros indica te w rite mode cs sclk sdi 00 a 5 a 4 a 3 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 x x data is moved t o a ddress www.austriamicrosystems.com/as3930 revision 1.0 18 - 33 as3930 data sheet - detailed description figure 15. send direct command byte 8.4 channel amplifier and frequency detector the channel amplifier consists of a variable gain amplifier (vga), an automatic gain control, and a frequency detector. the lat ter detects the presence of a carrier. as soon as the carrier is detected the agc is enabled, the gain of the vga is reduced and set to the rig ht value and the rssi can be displayed. 8.4.1 frequency detector / agc the frequency detection uses the rtc as time base. in case the internal rc oscillator is used as rtc, it must be calibrated, bu t the calibration is guaranteed for a 32.768 khz crystal oscillator only. the frequency detection criteria can be tighter or more relaxed accordi ng to the setup described in r2<1:0> (see table 13) . the agc can operate in two modes: agc down only (r1<5>=0) agc up and down (r1<5>=1) as soon as the agc starts to operate, the gain in the vga is se t to maximum. if the agc down only mode is selected, the agc can only decrease the gain. since the rssi is directly derived from the vga gain, the system holds the rssi peak. when the agc up and down mode is selected, the rssi can follow the input signal strength variation in both directions. regardless which agc operation mode is used, the agc needs maximum 35 carrier periods to settle. the rssi is stored in the register r10<4:0>. both agc modes (only down or down and up) can also operate with time limitation. this option allows agc operation only in time slot of 256s following the internal wake-up. then the agc (rssi) is frozen till the wake-up or rssi reset occurs. the rssi is reset either with the direct command 'clear_wakeup' or 'reset_rssi'. the 'reset_rssi' command resets only the agc s etting but does not terminate wake-up condition. this means that if the si gnal is still present the new agc setting (rssi) will appear not later than 300s (35 lf carrier periods) after the command was received. the agc setting is reset if for duration of 3 manchester half symbols n o carrier is detected. if the wake-up irq is cleared the chip will go back to listening mode. table 13. tolerance settings for wakeup r2<1> r2<0> tolerance 00 relaxed 0 1 tighter (medium) 1 0 stringent 11 reserved www.austriamicrosystems.com/as3930 revision 1.0 19 - 33 as3930 data sheet - detailed description in case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller st arting gain on the amplifier, according to the table 14 . in this way it is possible to reduce the false frequency detection. 8.4.2 antenna damper the antenna damper allows the chip to deal with higher field strength, it is enabled by register r1<4>. it consists of shunt re sistors which degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. in this way the resonator see s a smaller parallel resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amp lifier (the amplifier doesn't saturate in presence of bigger signals). table 15 shows the bit setup. 8.5 demodulator / data slicer the performance of the demodulator can be optimized according to bit rate and preamble length as described in table 16 and table 17 . table 14. bit setting of gain reduction r4<3> r4<2> r4<1> r4<0> gain reduction 0 0 0 0 no gain reduction 0001 n.a. 0 0 1 0 or 1 n.a. 0 1 0 0 or 1 -4db 0 1 1 0 or 1 -8db 1 0 0 0 or 1 -12db 1 0 1 0 or 1 -16db 1 1 0 0 or 1 -20db 1 1 1 0 or 1 -24db table 15. antenna damper bit setup r4<5> r4<4> shunt resistor (parallel to the resonator at 125 khz) 00 1 k 01 3 k 10 9 k 11 27 k table 16. bit setup for envelop detector for different symbol rates r3<2> r3<1> r3<0> symbol rate [manchester symbols/s] 0 0 0 4096 0 0 1 2184 0 1 0 1490 01 1 1130 1 0 0 910 1 0 1 762 1 1 0 655 1 1 1 512 www.austriamicrosystems.com/as3930 revision 1.0 20 - 33 as3930 data sheet - detailed description if the bit rate gets higher, the time constant in the envelop detector must be set to a smaller value, this means that higher n oise is injected because of the wider band. the next table is a rough indication of how the envelop detector looks like for different bit rates. by using proper data slicer settings it is possible to improve the noise immunity paying the penalty of a longer preamble. in fact if the data slice r has a bigger time constant it is possible to reject more noise, but every time a transmission occurs, the data slicer need time to settle. this s ettling time will influence the length of the preamble. table 17 gives a correlation between data slicer setup and minimum required preamble length. note: these times are minimum required, but it is recommended to prolong the preamble. the comparator of the data slicer can work only with positive or with symmetrical threshold (r3<6>). in addition the threshold can be 20 or 40 mv (r3<7>) in case the length of the preamble is an issue the data slicer can also work with an absolute threshold (r1<7>). in this case t he bits r3<2:0> would not influence the performance. it is even possible to reduce the absolute threshold in case the environment is not partic ularly noisy (r2<7>). 8.6 correlator after frequency detection the data correlation is only performed if the correlator is enabled (r1<1>=1). the data correlation consists of checking the presence of a preamble (on/off modulated carrier) followed by a certain pattern. after the frequency detection the correlator waits 16 bits (see bit rate definition in table 18 ) and if no preamble is detected the chip is set back to listening mode and the false-wakeup register (r13<7:0>) is incremented by one. to get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (on/off modulated ca rrier). the bit duration is defined in the register r7<4:0> according to the table 18 as function of the real time clock (rtc) periods. table 17. bit setup for data slicer for different preamble length r3<5> r3<4> r3<3> minimum preamble length [ms] 00 0 0.8 00 1 1.15 01 0 1.55 01 1 1.9 10 0 2.3 10 1 2.65 11 0 3 11 1 3.5 table 18. bit rate setup r7<4> r7<3> r7<2> r7<1> r7<0> bit duration in rtc clock periods bit rate (bits/s) symbol rate (manchester symbols/s) 0 0 0 1 1 4 8192 4096 0 0 1 0 0 5 6552 3276 0 0 1 0 1 6 5460 2730 0 0 1 1 0 7 4680 2340 0 0 1 1 1 8 4096 2048 0 1 0 0 0 9 3640 1820 0 1 0 0 1 10 3276 1638 0 1 0 1 0 11 2978 1489 0 1 0 1 1 12 2730 1365 0 1 1 0 0 13 2520 1260 0 1 1 0 1 14 2340 1170 www.austriamicrosystems.com/as3930 revision 1.0 21 - 33 as3930 data sheet - detailed description if the preamble is detected correctly the correlator keeps searching for a data pattern. the duration of the preamble plus the pattern should not be longer than 40 bits (see bit rate definition in table 18 ). the data pattern can be defined by the user and consists of two bytes which are stored in the registers r5<7:0> and r6<7:0>. the two bytes define the pattern consisting of 16 half bit periods. this means the patter n and the bit period can be selected by the user. the only limitation is that the pattern (in combination with preamble) must obey manchester coding and timing. it must be noted that according to manchester coding a down-to-up bit transition represents a symbol "0", while a trans ition up-to-down represents a symbol "1". if the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). msb has to be tra nsmitted first. the user can also select (r1<2>) if single or double data pattern is used for wake-up. in case double pattern detection is set, the same pattern has to be repeated 2 times. additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (r2<6:5>), a s shown in the table 19 . if the pattern is matched the wake-up interrupt is displayed on the wake outp ut. in case the manchester decoder is enabled (r1< 3>) the data coming out from the dat pin are decoded and the clock is recovered on the pin dat_cl. the data coming out from the dat pin are stable (and therefore can be acquired) on the rising edge of the cl_dat clock, as show n in figure 16 . 0 1 1 1 0 15 2184 1092 0 1 1 1 1 16 2048 1024 1 0 0 0 0 17 1926 963 1 0 0 0 1 18 1820 910 1 0 0 1 0 19 1724 862 1 0 0 1 1 20 1638 819 1 0 1 0 0 21 1560 780 1 0 1 0 1 22 1488 744 1 0 1 1 0 23 1424 712 1 0 1 1 1 24 1364 682 1 1 0 0 0 25 1310 655 1 1 0 0 1 26 1260 630 1 1 0 1 0 27 1212 606 1 1 0 1 1 28 1170 585 1 1 1 0 0 29 1128 564 1 1 1 0 1 30 1092 546 1 1 1 1 0 31 1056 528 1 1 1 1 1 32 1024 512 table 19. allowed pattern detection errors r2<6> r2<5> maximum allowed error in the pattern detection 0 0 no error allowed 0 1 1 missed zero 1 0 2 missed zeros 1 1 3 missed zeros table 18. bit rate setup r7<4> r7<3> r7<2> r7<1> r7<0> bit duration in rtc clock periods bit rate (bits/s) symbol rate (manchester symbols/s) www.austriamicrosystems.com/as3930 revision 1.0 22 - 33 as3930 data sheet - detailed description figure 16. synchronization of data with recovered manchester clock if the pattern detection fails the internal wake-up (on all active channels) is terminated with no signal sent to mcu and the f alse wakeup register will be incremented (r13<7:0>). the wake-up state is terminated with the direct command ?clear_wake? table 12 . this command terminates the mcu activity. the termination can also be automatic in case there is no response from mcu. the time out for automatic termination is set in a register r7<7:5 >, as shown in the table 20 . table 20. timeout setup r7<7> r7<6> r7<5> time out 000 0 sec 0 0 1 50 msec 0 1 0 100 msec 0 1 1 150 msec 1 0 0 200 msec 1 0 1 250 msec 1 1 0 300 msec 1 1 1 350 msec cl_dat dat www.austriamicrosystems.com/as3930 revision 1.0 23 - 33 as3930 data sheet - detailed description 8.7 wakeup protocol - ca rrier frequency 125 khz 8.7.1 without pattern detectio n (manchester decoder disabled) figure 17. wakeup protocol overview without pattern detection (only carrier frequency detection, manchester decoder disabled) in case the data correlation is disabled (r1<1>=0) the as3930 wakes up upon detection of the carrier frequency only as shown in figure 17 . in order to ensure that as3930 wakes up the carrier burst has to last longer than 550 s. to set as3930 back to listening mode the re are two possibilities: either the microcontroller sends the direct comm and clear_wake via sdi or the time out option is used (r7<7:5>). in case the latter is chosen,as3930is automatically set to listening mode after the time defined in t_out (r7<7:5>), counting starts at the low-to -high wake edge on the wake pin. 8.7.2 single pattern detectio n (manchester decoder disabled) the figure 18 shows the wakeup protocol in case the pattern correlation is enabled (r1<1>=1) for a 125 khz carrier frequency. the initial ca rrier burst has to be longer than 550 s and can last maximum 16 bits (see bit rate definition in table 18 ). if the on/off mode is used (r1<5>=1), the minimum value of the maximum carrier burst duration is limited to 10 ms. this is summarized in table 21 . in case the carrier burst is too long the internal wakeup will be set back to low and the false wakeup counter (r13<7:0>) will be incremented by one. the carrier burst must be followed by a preamble (0101... modulated carrier with a bit duration defined in table 18 ) and the wakeup pattern stored in the registers r5<7:0> and r6<7:0>. the preamble must have at least 4 bits and the preamble duration together with the pattern should not be longer than 40 bits. if the wakeup pattern is correct the signal on the wake pin is set to high and the data transmissio n can get started. to set the chip back to listening mode the direct command clear_false, as well as the time out option (r7<7:5>) can be used. www.austriamicrosystems.com/as3930 revision 1.0 24 - 33 as3930 data sheet - detailed description figure 18. wakeup protocol overview with single pattern detection (manchester decoder disabled) table 21. preamble requirements in standard mode, scanning mode and on/off mode bit rate (bit/s) maximum duration of the carrier burst in standard mode and scanning mode (ms) maximum duration of the carr ier burst in on/off mode (ms) 8192 1.95 10 6552 2.44 10 5460 2.93 10 4680 3.41 10 4096 3.90 10 3640 4.39 10 3276 4.88 10 2978 5.37 10 2730 5.86 10 2520 6.34 10 2340 6.83 10 2184 7.32 10 2048 7.81 10 1926 8.30 10 1820 8.79 10 1724 9.28 10 1638 9.76 10 1560 10.25 10.25 1488 10.75 10.75 1424 11.23 11.23 1364 11.73 11.73 1310 12.21 12.21 1260 12.69 12.69 www.austriamicrosystems.com/as3930 revision 1.0 25 - 33 as3930 data sheet - detailed description 8.7.3 single pattern detectio n (manchester decoder enabled) the figure 19 shows the wakeup protocol in case both the pattern correlation and the manchester decoder are enabled (r1<1>=1 and r1<3>=1) for a 125 khz carrier frequency. the initial carrier burst has to be at least 42 manchester symbols long and has to be followed by a separation bit (one bit of no-carrier). the carrier burst must be followed by a minimum 4 manchester symbol preamble (10101010) and the pattern stored in the r5<7:0> and r6<7:0>. the preamble can only be made up by integer manchester symbol and the preamble durat ion together with the pattern should not be longer than 40 bi ts. if the pattern is correct the si gnal on the wake pi n is set to hig h, the data are internally decoded and the manchester clock is recovered. to set the as3930 back to listening mode the direct command clear_fal se or the time out option (r7<7:5>) can be used. in case the on/off mode is enabled the manchester decoder can not be used . figure 19. wakeup protocol overview with single pattern detection (manchester decoder enabled) 8.8 false wakeup register the wakeup strategy in the as3930 is based on 2 steps: 1. frequency detection: in this phase the frequency of the received signal is checked. 2. pattern correlation: here the pattern is demodulated and checked whether it corresponds to the valid one. if there is a disturber or noise capable to overcome the first step (frequency detection) without producing a valid pattern, th en a false wakeup call happens.each time this event is recognized a counter is incremented by one and the respective counter value is stored in a memo ry cell (false wakeup register). thus, the microcontroller can periodically look at the false wakeup register, to get a feeling how noisy the surrounding environment is and can then react accordingly (e.g. reducing the gain of the lna during frequency detection, set the as3930 tem porarily to power down etc.), as shown in the figure 20 . the false wakeup counter is a useful tool to quickly adapt the system to any changes in the noise environment and thus avoid false wakeup events. 1212 13.20 13.20 1170 13.67 13.67 1128 14.18 14.18 1092 14.65 14.65 1056 15.15 15.15 1024 15.62 15.62 table 21. preamble requirements in standard mode, scanning mode and on/off mode bit rate (bit/s) maximum duration of the carrier burst in standard mode and scanning mode (ms) maximum duration of the carr ier burst in on/off mode (ms) www.austriamicrosystems.com/as3930 revision 1.0 26 - 33 as3930 data sheet - detailed description most wakeup receivers have to deal with environments that can rapidly change. by periodically monitoring the number of false wa keup events it is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full fle xibility of as3930. note: if the manchester decoder is enabled, the false wakeup register is not able to store the false wakeup events. figure 20. concept of false wakeup register together with system 8.9 real time clock (rtc) the rtc can be based on a crystal oscillator (r1<0>=1), the intern al rc-oscillator (r1<0>=0) or an external clock source (r1<0> =1). the crystal has higher precision of the frequency but a higher current consumption and needs three external components (crystal plu s two capacitors). the rc-oscillator is completely integrated and can be calibrated if a reference signal is available for a very sho rt time to improve the frequency accuracy. the calibration gets started with the trim_osc direct command. since no non-volatile memory is available on the chip, the calibration must be done every time after battery replacement. since the rtc defines the time base of the frequency detection, the selected frequency (frequency of the crystal oscillator or the reference frequency used for calibration of the rc oscillator) should be about one forth of the carrier frequency: f rtc ~ f car * 0.25 (eq 1) where: f car is the carrier frequency and f rtc is the rtc frequency note: the third option for the rtc is the use of an external clock source, which must be applied directly to the xin pin (xout floati ng). frequency detector pattern correlator wakeup level1 wakeup level2 wake false wakeup register unsuccessful pattern correlation register setup microcontroller read false wakeup register change setup to minimize the false wakeup events www.austriamicrosystems.com/as3930 revision 1.0 27 - 33 as3930 data sheet - detailed description 8.9.1 crystal oscillator 8.9.2 rc-oscillator to trim the rc-oscillator, set the chip select (cs) to high before sending the direct command trim_osc over sdi. then 65 digita l clock cycles of the reference clock (e.g. 32.768 khz) have to be sent on the clock bus (scl), as shown in figure 21 . after that the signal on the chip select (cs) has to be pulled down. the calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. in case the rc-osc illator is switched off or a power-on-reset happens (e.g. battery change) the calibration has to be repeated. figure 21. rc-oscillator calibration via sdi 8.9.3 external clock source to clock the as3930 with an external signal the crystal oscillator has to be enabled (r1<1>=1). as shown in the figure 3 the clock must be applied on the pin xin while the pin xout must stay floating. the rc time constant has to be 100 s with a tolerance of 10% (e.g. r=680 k and c=22pf). in the table 24 the clock characteristics are summarized. table 22. characteristics of xtal symbol parameter conditions min typ max units crystal accuracy (initial) overall accuracy 120 p.p.m. crystal motional resistance 60 k frequency 32.768 khz contribution of the oscillator to the frequency error 5 p.p.m start-up time crystal dependent 1 s duty cycle 45 50 55 % current consumption 1 a table 23. characteristics of rco symbol parameter conditions min typ max units frequency if no calibration is performed 27 32.768 42 khz if calibration is performed 31 32.768 34.5 khz calibration time periods of reference clock 65 cycles current consumption 200 na table 24. characteristics of external clock symbol parameter conditions min typ max units vi low level 0 0.1* v dd v vh high level 0.9*v dd v dd v www.austriamicrosystems.com/as3930 revision 1.0 28 - 33 as3930 data sheet - detailed description note: in power down mode the external clock has to be set to v dd . tr rise-time 3 s tf fall-time 3 s t=1/2 rc rc time constant 90 100 110 s table 24. characteristics of external clock symbol parameter conditions min typ max units www.austriamicrosystems.com/as3930 revision 1.0 29 - 33 as3930 data sheet - pack age drawings and markings 9 package drawings and markings the product is available in 16 pin tssop and qfn 4x4 16 ld packages. figure 22. package diagram 16 pin tssop table 25. package dimensions 16 pin tssop symbol min typ max symbol min typ max a 1.10 e 6.40 bsc a1 0.05 0.15 l 0.50 0.60 0.70 a2 0.85 0.90 0.95 a 0o 4o 8o aaa 0.076 n, p, p1 see variations b 0.19 - 0.30 variations : b1 0.19 0.22 0.25 d p p1 n bbb 0.10 aa/aat 2.90 3.00 3.10 1.59 3.2 8 c 0.09 - 0.20 ab-1/abt-1 4.90 5.00 5.10 3.1 3.0 14 c1 0.09 0.127 0.16 ab/abt 4.90 5.00 5.10 3.0 3.0 16 d see variations ac/act 6.40 6.50 6.60 4.2 3.0 20 e1 4.30 4.40 4.50 ad/adt 7.70 7.80 7.90 5.5 3.2 24 e 0.65 bsc ae/aet 9.60 9.70 9.80 5.5 3.0 28 www.austriamicrosystems.com/as3930 revision 1.0 30 - 33 as3930 data sheet - pack age drawings and markings note: 1. die thickness allowable is 0.279 0.0127. 2. dimensioning and tolerances conform to asme y14.5m-1994 . 3. datum plane h located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting lin e. 4. datum a-b and d to be determined where center line between leads exits plastic body at datum plane h. 5. d & e1 are reference datum and do not include mold flash or protrusions, and are measured at the bottom parting line. mold lash or pro - trusions shall not exceed 0.15mm on d and 0.25mm on e per side. 6. dimension is the length of terminal for soldering to a substrate. 7. terminal positions are shown for reference only. 8. formed leads shall be planar with respect to one another within 0.076mm at seating plane. 9. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.07mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and an adjacent lead should be 0.07mm for 0.65mm pitch. 10. section b-b to be determined at 0.10mm to 0.25mm from the lead tip. 11. dimensions p and p1 are thermally enhanced variations. values shown are maximum size of exposed pad within lead count and body size. end user should verify available size of exposed pad for specific device application. 12. all dimensions are in millimeters, angle is in degrees. 13. n is the total number of terminals. www.austriamicrosystems.com/as3930 revision 1.0 31 - 33 as3930 data sheet - pack age drawings and markings figure 23. package diagram qfn 4x4 16 ld note: 1. die thickness allowable is 0.279 0.0127. 2. dimensioning and tolerances conform to asme y14.5m-1994 . 3. dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. dimension l1 repres ents terminal full back from package edge up to 0.1mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional table 26. package dimensions qfn 4x4 16 ld symbol min typ max symbol min typ max a 0.75 0.85 0.95 e 0.65 bsc a1 0.203 ref l 0.40 0.50 0.60 b 0.25 0.30 0.35 l1 0.10 d 4.00 bsc p 45o bsc e 4.00 bsc aaa 0.15 d2 2.30 2.40 2.50 ccc 0.10 e2 2.30 2.40 2.50 #1 2 3 4 56 7 8 9 10 11 12 16 15 14 13 www.austriamicrosystems.com/as3930 revision 1.0 32 - 33 as3930 data sheet - revision history revision history table 27. revision history revision date owner description 1.0 07/10/09 rlc www.austriamicrosystems.com/as3930 revision 1.0 33 - 33 as3930 data sheet - ordering information 10 ordering information copyrights copyright ? 1997-2009, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact table 28. ordering information ordering code type marking delivery form 1 1. dry pack sensitivity level =3 according to ipc/jedec j-std-033a for full reels. note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor delivery quantity AS3930-BTST 16 pin tssop as3930 7 inches tape&reel 1000 pcs as3930-bqft qfn 4x4 16 ld as3930 7 inches tape&reel 1000 pcs |
Price & Availability of AS3930-BTST
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |